1. Field of the Invention
The present invention generally relates to data communications in a computer system and, more particularly, to memory control design to support synchronous Dynamic Random Access Memory (DRAM) type memory.
2. Description of Related Art
In conventional central processing unit (CPU) designs, speed in which data is transferred within the CPU has been increasing rapidly with the advent Reduced Instruction Set Computer (RISC) architectures and even more so due to extensive use of pipelining. However, unlike the CPU development, development of different types of memory has concentrated on increasing media density in order to reduce the cost per bit of memory and not speed. This disparity has created an imbalance in memory bandwidth required for small low-cost systems. External interleaving to improve memory bandwidth has been employed to overcome this problem, but has failed. External interleaving has become a less favorable option due to use of asynchronous interfaces, high timing margins, high data rate, and a lack of registers for control signals, addresses and Input/Output's. The cost of external interleaving is also high due to additional glue logic and total memory density required for a given bandwidth. This imbalance created the need for synchronous DRAM-type memory units (syncDRAMs).
SyncDRAMs offer extensive memory density with low cost and high bandwidth memory architecture. Furthermore, syncDRAMs are able to support various applications like mainstore, peripherals, graphics and video. SyncDRAMs are designed for a wide range of applications with programmable features such as latency, burst length and burst-type. They can support single or dual bank high frequency and low power operations.
A key feature provided by syncDRAMs is immediate access to multiple blocks of data called "bursts." Burst length refers to the number of words that will be output or input in a read or write cycle respectively. After a read burst has completed, the output bus will become high impedance. The burst length is programmable as 1, 2, 4 or 8 words, or full page. The ability of the CPU to access these bursts of information gives the CPU access to wider bandwidth of memory.
In operation, the syncDRAM is enabled by a command from a memory control unit responding to a data transfer request from the CPU. The syncDRAM responds by enabling an internal clock (CKE#) to begin the command cycle when the clock enable pin is asserted. An address is then internally latched by the syncDRAM from which data will be read or written to. Each time a burst of data is requested, the syncDRAM must go through the initiation sequence in order to access the address from which data will be read or written. The time it takes to complete the initiation process will deficit the overall memory retrieval time needed to access the data.
Accordingly, it would be of great use to a computer industry to further speed up the already efficient syncDRAM memories by reducing the time it takes to access the syncDRAMs by reducing the time it takes to initiate the data retrieving cycle. In the event data is not ready to be transferred, conventional implementations require a second request to send data to or read data from the syncDRAM when the data is ready. This requires a second read or write request which requires initializing the syncDRAM again. Being able to hold the syncDRAM idle and initiated until data is ready would greatly speed up data transfer in the syncDRAM by allowing wait states when data is not ready, so that devices of different speeds than the syncDRAM can adjust. As will be seen, the present invention achieves this in an elegant and cost effective manner.